The present invention relates to error detection and error correction, and more particularly to an error correction system for a memory device, capable of correcting a block error which is produced in a relatively large storage area.
A memory device, for example, a semiconductor memory device usually has an error checking/correcting function. The error correcting function is performed in such a manner that an error correction code is applied or added to data in a recording operation, and the error correction code of reproduced information is checked to detect and correct an error.
As regards the error correction code, there are known codes for correcting a random error, such as the Hamming code and codes for correcting a block error, such as the Fire code. Each of memory devices is made up of a multiplicity of memory elements, a peripheral circuit and a packaging system therefor, and memory devices are not always equal to each other in abnormality/failure occurring position. That is, the memory devices have different error-distribution patterns. The error is roughly classified into a single or random error caused by the abnormality or failure which occurs in abnormality or failure which occurs in the peripheral circuit or the packaging system. Accordingly, it is desirable that a memory device has a function of correcting both the random error and the block error. However, conventional error correction codes fail in the efficient, inexpensive correction of both of these errors.
An error correction system has been proposed in Chen Chin-Long U.S. Pat. No. 4,509,172 issued Apr. 2, 1985 which is applied in a memory device such that a plurality of bits making up one word are allotted to memory chips, and can detect not only a single bit error but also a multiple error (so-called escape error). In this prior art system, a syndrome bit generator uses a special H-matrix designed so that the syndrome of a multiple bit error produced in a memory chip does not coincide with any syndrome of a single bit error produced in the memory chip, and delivers a syndrome on the basis of the special H-matrix and a word read from the memory device, to determine whether an error existing in the read-out word is a single bit error or a multiple bit error. Although the above system can prevent a multiple bit error from being erroneously detected as a single bit error, only the single bit error can be corrected. In other words, it is not intended for the system to correct both the single bit error and the multiple bit error.